A skew is in parallel data transmission the difference in arrival time of data bits transmitted at the same time. The skew between single data lines of a parallel interface, for example of DRAM memory chips, is an obstacle for increasing the data transfer rate.
FIG. 1A shows an ideal case of data bits received by the receiver via a parallel interface, wherein all data bits are perfectly aligned in time. As can be seen from FIG. 1A, there is in a data period a time margin for correctly sampling the data bits in parallel in one time instant.
As can be seen from FIG. 1B, when a skew occurs during data transfer within the time margin for directly sampling all data bits in parallel in one time instant is reduced until no common sampling point for all data bits can be determined anymore as shown in FIG. 1C. In the given example, data bit 1 shows an increased skew and data bit n shows a negative skew with respect to data bit 0. In the situation as shown in FIG. 1C, a skew related transmission failure occurs on the receiving side. If the skew becomes even bigger, this can lead to a sampling of false data bits due to the skew as shown in FIG. 1D. As can be seen from FIG. 1D, data bit 1 is too late, whereas data bit 2 is too early with respect to the correct sampling time at the receiver. As data transfer rates increase, word duration and margin decrease limiting the maximum amount of allowed skew. The skew can be generated by a static effect like trace length differences or mismatch in circuits which are constant during operation time of the system as well as dynamic effects like temporary supply voltage variations, temperature drift and clock jitter which change skew during operation of the system.
It is an object of the present invention to provide a method and an apparatus for determining a skew of data bits received by a receiver via an interface from a transmitter.